Integrated circuit chips are conventionally enclosed in a package that provides protection from environmental conditions. One form of package is a leadless package having a carrier that defines an interface for electrical connection to other devices. Another form of package is a leaded package having leads that enable electrical interconnection between the chip and another electrical component, such as a printed circuit board or a motherboard. One such leaded semiconductor package is a Quad Flat Package including a supporting leadframe, one or more chips electrically coupled to the leadframe, encapsulating material molded over the leadframe and the chip(s), and multiple leads extending from the encapsulating material.
The leadframe is stamped or etched from metal to include the die pad or island, tiebars extending from die pad, a power bar, and a ground ring configured to communicate with die pad, and the leads. The leads include input/output leads, at least one lead coupled to the power bar, and at least one lead coupled to the ground ring. Connectors are suitably wired between the leads and the chip. The power bar and the ground ring are connected to predefined leads. As a consequence, and by necessity, some of the leads are connected to power bar and some of the leads are connected to ground ring. Utilizing the leads to connect with the power bar and/or the ground ring undesirably reduces the number of remaining and available input/output leads for forming an electrical pathway to chip. In addition, each new chip layout calls for a different leadframe design.
For these and other reasons there is a need for the present invention.